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BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
Rev. 01 -- 14 May 2009 Product data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect power transistor in SO20. Device is manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring very low on-state resistance, integrated current sensing transistors and over temperature protection diodes.
1.2 Features and benefits
Integrated current sensor Integrated temperature sensor
1.3 Applications
Lamp switching Motor drive systems Power distribution Solenoid drivers
1.4 Quick reference data
Table 1. Quick reference Conditions VGS = 5 V; ID = 5 A; Tj = 25 C; see Figure 16; see Figure 17 Tj = 25 C; VGS = 5 V; see Figure 18 Tj = 25 C; VGS = 0 V; ID = 250 A Min Typ 21.3 Max 25 Unit m Symbol Parameter RDSon drain-source on-state resistance ratio of drain current to sense current
Static characteristics, FET1 and FET2
ID/Isense
5130 55
5700 -
6270 -
A/A V
V(BR)DSS drain-source breakdown voltage
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
2. Pinning information
Table 2. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pinning information Symbol G1 IS1 D1 A1 C1 G2 IS2 D2 A2 C2 D2 KS2 S2 S2 D2 D1 KS1 S1 S1 D1 Description gate 1 current sense 1 drain 1 anode 1 cathode 1 gate2 current sense 2 drain2 anode 2 cathode 2 drain2 Kelvin source 2 source 2 source 2 drain2 drain 1 Kelvin source 1 source 1 source 1 drain 1
1 10 20 11 D1 A1 D2 A2
Simplified outline
Graphic symbol
FET1
FET2
SOT163-1 (SO20)
G1
IS1 S1 KS1 C1 G2
IS2 S2 KS2 C2
003aaa745
3. Ordering information
Table 3. Ordering information Package Name BUK9MPP-55PRR SO20 Description plastic small outline package; 20 leads; body width 7.5 mm Version SOT163-1 Type number
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
2 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature Tsp = 25 C; VGS = 5 V; see Figure 2; see Figure 3; [1][2] Tsp = 100 C; VGS = 5 V; see Figure 3; Tsp = 25 C; tp 10 s; pulsed; see Figure 3 Tsp = 25 C; see Figure 1 [1][2] Conditions 25 C < Tj < 150 C RGS = 20 k; 25 C < Tj < 150 C Min -15 -55 -55 Max 55 55 15 9.16 5.8 144 3.9 150 150 100 Unit V V V A A A W C C V
In accordance with the Absolute Maximum Rating System (IEC 60134).
Limiting values, FET1 and FET2
Visol(FET-TSD) FET to temperature sense diode isolation voltage Source-drain diode, FET1 and FET2 IS ISM EDS(AL)S source current peak source current Tsp = 25 C; tp 10 s; pulsed; Tsp = 25 C [3][4] [5] [2]
-
5.5 144 323
A A mJ
Avalanche ruggedness, FET1 and FET2 non-repetitive ID = 9.16 A; Vsup 55 V; VGS = 5 V; Tj(init) = 25 C; drain-source avalanche unclamped inductive load; see Figure 4; energy electrostatic discharge voltage HBM; pins 3, 16, 20 to pins 1, 2, 17, 18 and 19 shorted HBM; pins 8, 11, 15 to pins 6, 7, 12, 13 and 14 shorted HBM; C = 100 pF; R = 1.5 k; all pins
[1] [2] [3] [4] [5] Single device conducting. Current is limited by chip power dissipation rating. Single-pulse avalanche rating limited bymaximum junction temperature of 150 C Repetitive rating defined in avalanche rating figure Refer to application note AN10273 for further information
Electrostatic discharge, FET1 and FET2 VESD 4 4 0.15 kV kV kV
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
3 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
120 Pder (%) 80
003aab388
12 ID (A)
003aac531
8
40
4
0 0 50 100 150 Tsp 200 (C)
0 0 50 100 150 Tsp (C) 200
Fig 2. Fig 1. Normalized total power dissipation as a function of solder point temperature, FET1 and FET2
Continuous drain current as a function of solder point temperature, FET1 and FET2
103 ID (A) 102 Limit R DS on = VDS / ID
003aac464
tp = 10 s
10
100 s
1 ms 1 DC 10-1 10 ms 100 ms
10-2 10-1
1
10
VDS (V)
102
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and FET2
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
4 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
102 IAL (A)
003aac526
10
(1)
(2)
1
(3)
10-1 10-3
10-2
10-1
1
tAL (ms)
10
Fig 4.
Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and FET2
5. Thermal characteristics
Table 5. Symbol Rth(j-sp) Rth(j-a) Thermal characteristics Parameter Conditions Min Typ 73 Max 32 32 Unit K/W K/W K/W thermal resistance from FET1 junction to solder point FET2 thermal resistance from mounted on printed circuit board; Both junction to ambient channel conducting; zero heat sink area; see Figure 5; see Figure 6 mounted on printed circuit board; Both channel conducting; 200 mm2 copper heat sink area; see Figure 5; see Figure 7 mounted on printed circuit board; Both channel conducting; 400 mm2 copper heat sink area; see Figure 5; see Figure 8 mounted on printed circuit board; One channel conducting; zero heat sink area; see Figure 5; see Figure 6 mounted on printed circuit board; One channel conducting; 200 mm2 copper heat sink area; see Figure 5; see Figure 7 mounted on printed circuit board; One channel conducting; 400 mm2 copper heat sink area; see Figure 5; see Figure 8
-
60
-
K/W
-
51
-
K/W
-
105
-
K/W
-
90
-
K/W
-
78
-
K/W
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
5 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
120 Rth(j-a) (K/W) (1) 80 (2)
003aac472
40
001aae478
Fig 6.
PCB used for thermal tests; zero heat sink area
0 0 100 200 300 A (mm2) 400
Fig 5.
Thermal resistance from junction to ambient as a function of printed-circuit board (PCB) heat sink area
001aae479
001aae480
Fig 7.
PCB used for thermal tests; heat sink area 200 mm2
Fig 8.
PCB used for thermal tests; heat sink area 400 mm2
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
6 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
102 Zth(j-mb) (K/W) 10
= 0.5
0.2 0.1 0.05 0.02
003aad207
1
P = tp T
10-1
tp t T
10-2 10-6
single shot
10-5
10-4
10-3
10-2
10-1
1
10
102
103
tp (s) 104
Fig 9.
Transient thermal impedance from juction to ambient as a function of pulse duration, FET1 and FET2 (PCB used for thermal tests;heat sink area 400mm2)
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 A; VGS = 0 V; Tj = 25 C ID = 250 A; VGS = 0 V; Tj = -55 C ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 14; see Figure 15 ID = 1 mA; VDS = VGS; Tj = 150 C; see Figure 14; see Figure 15 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 14; see Figure 15 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 40 V; VGS = 0 V; Tj = 25 C VDS = 40 V; VGS = 0 V; Tj = 150 C VDS = 0 V; VGS = 15 V; Tj = 25 C VGS = 5 V; ID = 5 A; Tj = 25 C; see Figure 16; see Figure 17 VGS = 5 V; ID = 5 A; Tj = 150 C; see Figure 16; see Figure 17 VGS = 4.5 V; ID = 5 A; Tj = 25 C; see Figure 16; see Figure 17 VGS = 10 V; ID = 5 A; Tj = 25 C; see Figure 16; see Figure 17 ID/Isense SF(TSD) ratio of drain current to sense current temperature sense diode temperature coefficient Tj = 25 C; VGS = 5 V; see Figure 18 IF = 250 A; 25 C < Tj < 150 C; see Figure 19 Min 55 50 1 0.5 5130 -5.4 Typ 1.5 0.02 2 21.3 23.7 20.2 5700 -5.7 Max 2 2.3 3 125 300 25 46.8 27.9 22.6 6270 -6 Unit V V V V V A A nA m m m m A/A mV/K
Static characteristics, FET1 and FET2
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
7 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
Table 6. Symbol VF(TSD)
Characteristics ...continued Parameter temperature sense diode forward voltage total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time internal drain inductance internal source inductance source-drain voltage reverse recovery time recovered charge From pin to centre of die From source lead to source bonding pad VDS = 30 V; RL = 3 ; VGS = 5 V; RG(ext) = 10 VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 C; see Figure 21 Conditions IF = 250 A; Tj = 25 C; see Figure 19 Min 2.855 Typ 2.9 Max 2.945 Unit V
Dynamic characteristics, FET1 and FET2 QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf LD LS ID = 5 A; VDS = 44 V; VGS = 5 V; see Figure 20 23 3.4 8.8 1736 244 93 29 50 91 46 0.85 1.9 2315 293 127 nC nC nC pF pF pF ns ns ns ns nH nH
Source-drain diode, FET1 and FET2 VSD trr Qr IS = 5 A; VGS = 0 V; Tj = 25 C; see Figure 22 IS = 5 A; dIS/dt = -100 A/s; VGS = -10 V; VDS = 30 V 0.85 44 69 1.2 V ns nC
100 ID (A) 80 10 5 4.5 4
003aac457
50 RDS on (m) 40
003aac463
60
3.5 30
40
3 20
20
VGS (V) = 2.5
0 0 2 4 6 8 VDS (V) 10
10 2 4 6 8 VGS (V) 10
Fig 10. Output characteristics: drain current as a function of drain-source voltage; typical values, FET1 and FET2
Fig 11. Drain-source on-state resistance as a function of gate-source voltage; typical values, FET1 and FET2
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
8 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
50 gfs (S ) 40
003aac460
25 ID (A) 20
003aac465
15 30 10 20 5
Tj = 150 C 25 C
10 0 10 20 30 I D (A) 40
0 0 1 2 3 4 VGS (V) 5
Fig 12. Forward transconductance as a function of drain current; typical values, FET1 and FET2
Fig 13. Transfer characteristics; drain current as a function of gate-source voltage; typical values, FET1 and FET2
10-1 ID (A)
003aac894
2.5 VGS(th) (V) 2.0 max
003aac895
10-2 min typ max
1.5
typ
10-3
1.0
min
10-4
0.5
10-5
0 -60
10-6 0 60 120 Tj (C) 180 0 1 2 VGS (V) 3
Fig 14. Gate-source threshold voltage as a function of junction temperature, FET1 and FET2
Fig 15. Sub-threshold drain current as a function of gate-source voltage, FET1 and FET2
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
9 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
80 RDS on (m) 2.5 60 3
003aac462
2.0 a
001aae823
3.5
1.5
4 40 4.5 5 20 VGS (V) = 10
0.5 1.0
0 0 20 40 60 80 I D (A) 100
0 -60
0
60
120 Tj (C)
180
Fig 16. Drain-source on-state resistance as a function of drain current; typical values, FET1 and FET2
Fig 17. Normalized drain-source on-state resistance factor as a function of junction temperature, FET1 and FET2
3.0 VF(TSD) (V)
001aae485
7000 ID/Isense 6500
003aac459
2.5
6000
2.0
5500
5000 2 4 6 8 VGS (V) 10
1.5 0 40 80 120 Tj (C) 160
Fig 18. Ratio of drain current to sense current as a function of gate-source voltage; typical values, FET1 and FET2
Fig 19. Temperature sense diode forward voltage as a function of junction temperature; typical values, FET1 and FET2
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
10 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
5 VGS (V) 4 VDS = 14 V 3 VDS = 44 V
003aac461
104 C (pF)
003aac458
Cis s 103
Cos s 2 102 1 Crs s
0 0 10 20 30 QG (nC) 40
10 10-1
1
10
VDS (V)
102
Fig 20. Gate-source voltage as a function of turn-on gate charge; typical values, FET1 and FET2
Fig 21. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values, FET1 and FET2
003aac466
25 IS (A) 20 150 C 15 Tj = 25 C 10
5
0 0 0.5 1 1.5 VS D (V) 2
Fig 22. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET1 and FET2
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
11 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
7. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
8o o 0
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 23. Package outline SOT163-1
BUK9MPP-55PRR_1 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
12 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
8. Revision history
Table 7. Revision history Release date 20090514 Data sheet status Product data sheet Change notice Supersedes Document ID BUK9MPP-55PRR_1
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
13 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
BUK9MPP-55PRR_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 14 May 2009
14 of 15
NXP Semiconductors
BUK9MPP-55PRR
Dual TrenchPLUS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 6 5 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .13 Legal information. . . . . . . . . . . . . . . . . . . . . . . .14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Contact information. . . . . . . . . . . . . . . . . . . . . .14
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 May 2009 Document identifier: BUK9MPP-55PRR_1

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